AJIT GOPALAKRISHNAN ----------------------------------------------------------------------------------------------------------------------------------------- 2329 Champion Court, Raleigh, NC 27606 Tel: [Mobile] (919) 412 1820 Email: ajit.gopalakrishnan@gmail.com Web:http://www.ajitgopalakrishnan.com/ ----------------------------------------------------------------------------------------------------------------------------------------- OBJECTIVE To obtain a challenging full-time position as an Analog and Mixed-Signal Design Engineer EDUCATION * North Carolina State University, Raleigh, NC GPA: 4.00 # M.S. with thesis candidate, Electrical Engineering # Expected Graduation: May 2008 # Title: Investigation of techniques for optimization of lock range of Injection-locked frequency divider circuits # Advisor: Dr. Kevin G. Gard, Radio Analysis and Design (RAD) group, Dept. of ECE, NCSU * Vivekanand Education Society's Institute of Technology(VESIT),Mumbai, India (University of Mumbai) Bachelor of Engineering (B.E.), Electronics with distinction July 2005 Rank in college: 1 WORK EXPERIENCE Product Engineering Intern May 2006 to Aug. 2006 Product and Test Engineering group, Qualcomm Inc., San Diego # Worked on Agilent ATE and Agilent 93000 SOC testing software for debugging MSM 6260,MSM 7200 and MSM 7500 chipsets. # Worked with Failure Analysis Teams to identify potential leakage problems in chip design. # Collected and analyzed data obtained from characterization and correlation of MSM devices. # Assisted senior product engineers with analysis of reliability, qualification and yield data. TECHNICAL KNOWLEDGE AND SKILLS Programming Languages: C, C++, Assembly (8085, 8086, 8051), Perl HDLs: VHDL, Verilog EDA Tools used: Cadence DF II (Analog Artist, Virtuoso XL, DIVA, Verilog - XL, Encounter, HSPICE, SpectreRF, Awaves); Agilent ADS; Synopsys (Primetime, Design Compiler); ISETCAD; OrCAD Suite for IC Design (PSPICE, Layout Plus, Capture CIS); LASI; Xilinx ISE FPGA Design Flow; Agilent 93000 SOC series IC test suite Software packages: MATLAB, Dreamweaver, Adobe Photoshop, Adobe Pagemaker, COREL DRAW Operating Systems: Windows 98/2000/XP, Linux, Sun Solaris 8.0 GRADUATE COURSEWORK # Analog/RF: Analog Electronics, RF Design for Wireless, Independent Study on Analog-to-Digital Converter Performance Trends, IC Design for Wireless Communications, Integrated Bio-electronic Circuits, Data Converters # Digital: VLSI Systems Design, Digital ASIC Design, Digital Electronics # Device Physics: Nanotechnology frontiers, Principles of MOS Transistors TEACHING EXPERIENCE Graduate Teaching Assistant, ECE Dept., NCSU Grading final deliverables, instruction of students, designing & maintaining course webpages # Teaching Assistant for ECE 511 Analog Electronics Aug. 2007 to Dec 2007 # Teaching Assistant for ECE 792X IC Design for Wireless Commns. Jan. 2007 to May 2007 # Teaching Assistant for ECE 549 RF Design for Wireless Aug. 2006 to Dec 2006 # Teaching Assistant for ECE 435 Elements of Control Aug. 2005 to May 2006 # Teaching Assistant for ECE 331 Principles of Electrical Engineering I Aug. 2005 to Dec. 2005 TAPEOUTS (For details: www.ajitgopalakrishnan.com/tapeout) # Low-power signal-conditioning circuitry for an Intraocular Pressure Sensor in AMI 0.5µm process Worked in a team of three to design and layout a low-power, single-chip solution consisting of an Instrumentation Amplifier (Class-AB output stage op-amps), a Voltage-to-Frequency converter (a comparator and an integrator) and a PPM circuit with 340µW power consumption. PROJECTS UNDERTAKEN (For details: www.ajitgopalakrishnan.com/projects) * Graduate # Design of a 2Gbps CMOS transceiver in a 0.18μ process with a fully-differential architecture to drive a 75-cm lossy transmission line and a single-tap equalizer to minimize ISI. (power: 7mW, tD-Q/tD-Qbar ≤ 500ps, Eye opening: 400ps horizontal, 100mV vertical, Test sequence: 128 bit with maximum run-length of 5.) # Design of a 2GHz hybrid-latch flipflop (HLFF) in a 0.18μ process (power: 1.9mW, tD-Q/tD-Qbar ≤ 500ps) # Investigation of crest factor reduction algorithms for improving power amplifier linearity # Design of a 12-bit 25-MS/sec 57 mW CMOS Pipelined ADC as part of a team of three for satellite applications in a 0.18μ process consisting of a gain-boosted folded cascode amplifier with switched-capacitor CMFB circuit, high-speed dynamic comparators and digital error correction circuits. # Design of a CMOS Wireless Transmitter in a 0.18μ process including a Class-A power amplifier (Pout: 5dBm, IM3: -46dBc), upconversion mixer (10MHz ->5GHz, IM3: -56dBc) and a differential-to-single ended converter # Analysis of performance trends in ADC architectures to examine the tradeoffs involved between resolution, sampling frequency and power in the selection of ADC’s for specific applications. # Design and modeling of 22nm NMOS devices with a high-κ dielectric and extension junctions for Si, GaAs and InGaAs substrates in ISE-TCAD (Reported Ion/Ioff ratios of 79.8, 171 and 12 respectively) # Design of an utterance matcher in Verilog HDL for a Speech Recognition ASIC as part of a team of two and synthesized the design with Synopsys Design Compiler (delay 12ns) # Design and layout of transistor-level circuits of the Execute stage of a 32-bit Pipelined Microprocessor (DLX architecture) with a conditional carry-select fast adder # Design of a CMOS fully-differential operational amplifier in TSMC 0.18μ technology over process and temperature including CMFB, bias & compensation circuits (gain: 106dB, fT: 217MHz * Undergraduate # Dual-Resolution Digital Camera implemented in Programmable hardware Final-year project # Implementation of Wavelet-based Image Compression in VHDL Fall 2004 HONORS AND LEADERSHIP ACTIVITIES # Inducted to Phi Kappa Phi, the nation’s largest all discipline honor society # Ranked 104 among 37,000 candidates in the All-India IIT-GATE 2005 examination # Recipient of the prestigious Ratan-Tata Scholarship for the years 2002-2003 and 2003-2004 # Recipient of ‘Best Paper’ awards for the following technical papers ‘Extreme Ultraviolet Lithography’ ‘FinFET: An Improvement over conventional Double-Gate MOSFET structures’ # Editor of ‘Intelect’ and ‘E-M@il’ , society technical publications (2003-05) # Served on the management committee of PRAXIS – an inter-collegiate technical festival. REFERENCES Available on Request ---------------------------------- Willing to relocate